Digital integrated circuit chips are composed of many millions of gates that make up various functional components on a chip such as flip-flops, multiplexors, logic circuits, etc. A given chip design may have thousands of flip-flops scattered throughout the chip.
In order to effectively and efficiently test a given chip, certain test features are typically incorporated into the chip design for testing purposes. Before a chip is actually taped out and manufactured, the chip design is first simulated in software using various simulation tools such as, for example, an Automatic Test Pattern Generation (ATPG) tool. By simulating the design of the chip, the design features of the chip may be thoroughly tested before the expense and time of actually manufacturing the chip is incurred.
Pattern verification is a critical phase in testing of chips. A scan pattern is a digital string of binary ones and zeros that may be shifted through a scan chain of flip-flops in the chip design. Every scan pattern cycle is composed of two phases. The first phase is the load-unload phase where new data is shifted into the scan chains of flip-flops. The second phase is the capture phase where the data is captured into the flip-flops by applying a clock pulse.
Typically, the flip-flops in a digital integrated circuit design are designed such that they have normal data inputs and outputs (D and Q) and test inputs such as TI (test data input) and TE (test enable input). During simulation, the flip-flops may be placed in the scan test mode by enabling the TE input. Data may then be clocked into the flip-flops through the TI input instead of the normal D data input. During scan testing, the flip-flops of the chip are chained together to form multiple scan chains. The output Q of a given flip-flop is connected to the input TI of a next flip-flop. Each scan chain may comprise, typically, 5000 to 10,000 flip-flops.
The length of the load_unload phase is equal to the length of the longest scan chain of flip-flops. In multimillion gate designs, the longest chain may have thousands of flip-flops. Most of the time simulating the scan patterns through the scan chains is spent shifting the data into and out of the scan chains. To ensure proper behavior of the scan chains, the first test applied to the chip design is Chain Test which consists of shifting in and out a predetermined bit pattern (e.g., 0011).
Timing analysis may be performed on the simulation of the design of the chip by using external scan test clocks to clock the various clock domains (flip-flops and other digital logic that use a same clock). For every clock domain, an external scan test clock may be input at a port of the chip and used to clock the corresponding clock domain by by-passing the corresponding internal clock for the clock domain. The timing analysis identifies any capture mode violations such that the design may be fixed to eliminate the violations. However, such simulation and testing often require many scan test clocks using many ports of the chip in order to test all of the clock domains, especially for large chips with millions of gates. Even if certain ports of the chip are externally tied together at the chip level to the same scan clock, a single port of the chip is still needed for each clock domain within the chip. In the capture mode during timing analysis, scan patterns are clocked into the D inputs of the flip-flops instead of the TI inputs.
One of the major issues in generating tests for multi-million gate chip designs is how to reduce ATPG pattern count in order to fit in the tester memory. Designs with multiple clock domains pose a great challenge given that, by default, ATPG tools toggle one clock at a time during a capture mode. The number of scan clocks that may be required to be provided from the chip level may be very large if the chip design has a large number of internal clock domains. Each scan clock operates at the same frequency using the same waveform. Some clock domains may be grouped together solely based on designer input, but this has proven to cause timing problems if the clock domains that are grouped are not truly independent (i.e., share no data paths).
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.